1. Field of the Invention
This invention relates to current feedback amplifiers. More particularly, this invention relates to circuitry to eliminate the peaking of gain at high frequencies due to parasitic capacitance at the negative, or inverting input terminal of a current feedback amplifier.
2. Description of the Related Art
FIG. 1 shows a conventional current feedback amplifier circuit. The circuitry includes an input stage formed by two complementary buffers including four transistors 101-104, two current sources 106 and 108 and two current mirrors 120 and 130. The circuitry further includes an output stage formed by output buffer 140. Feedback for the amplifier is provided by an external feedback resistor R.sub.F, while gain is controlled by a gain control resistor R.sub.G and compensation is provided by capacitor C.sub.COMP.
In the input stage, the transistors 101 and 102 are complementary and have bases connected to serve as a positive input terminal V.sub.IN+ for the amplifier. The collector of transistor 101 is connected to a negative power supply V-, while the collector of transistor 102 is connected to a positive power supply V+. Transistors 101 and 102 are biased into conduction by current sources 106 and 108 connected to their respective emitters. The emitter follower transistors 103 and 104 of the input stage each have a base connected to an emitter of a complementary transistor in transistors 101 and 102 and an emitter connected to a negative, or inverting input terminal V.sub.IN-. The current mirrors 120 and 130 of the input stage have inputs I.sub.IN connected to respective collectors of the second pair of transistors 103 and 104 and outputs I.sub.OUT which mirror currents at their respective inputs I.sub.IN connected to form a gain node G.
The output buffer 140 is connected between gain node G and the amplifier output terminal V.sub.OUT. The feedback resistor R.sub.F is connected between the amplifier output terminal V.sub.OUT and V.sub.IN-. The gain control resistor R.sub.G connects from the negative input terminal V.sub.IN- to ground to control amplifier gain.
A capacitance C.sub.IN is not intentionally connected, but is a parasitic capacitance from V.sub.IN- to ground. Compensation capacitor C.sub.COMP is intentionally connected from the high capacitance gain node G to ground to control the gain vs. frequency characteristics of the amplifier.
In operation, transistors 101-104 buffer the voltage at V.sub.IN+ and present it to V.sub.IN-. An error current is provided at the negative input terminal V.sub.IN- by resistors R.sub.F and R.sub.G which form a voltage divider feedback circuit to divide the voltage at the amplifier output terminal V.sub.OUT to provide a divided voltage V.sub.OUT R.sub.G /(R.sub.G +R.sub.F). For a given output voltage at V.sub.OUT, the error current flows into or out of the feedback circuit through V.sub.IN- when the voltage at V.sub.IN- deviates from the divided voltage, V.sub.OUT R.sub.G /(R.sub.G +R.sub.F).
With increasing frequency, capacitances have an increasing effect on gain. Compensation capacitor C.sub.COMP is provided to dominate other capacitances in the circuitry to control the amplifier gain characteristics with increasing frequency as shown by curve 202 of FIG. 2. With C.sub.COMP, gain drops to the 3 dB bandwidth point at f=1/(2.pi.C.sub.COMP R.sub.F) as shown. As increased bandwidth is desired, C.sub.COMP is reduced toward the value of C.sub.IN. With C.sub.COMP approaching C.sub.IN, however, C.sub.IN begins to affect the amplifier output causing undesirable gain peaking beyond the expected 3 dB bandwidth of 1/(2.pi.C.sub.COMP R.sub.F) as shown by curve 204 in FIG. 2. It is thus desirable to utilize circuitry to compensate for C.sub.IN.
U.S. Pat. No. 5,418,495 entitled "Input Stage Improvement For Current Feedback Amplifiers", incorporated herein by reference, discloses circuitry for compensating for the capacitance C.sub.IN in a current feedback amplifier. FIG. 3 illustrates circuitry for compensating for the capacitance C.sub.IN as disclosed in U.S. Pat. No. 5,418,495. The circuitry of FIG. 3 includes components carried over from FIG. 1 with modifications. For convenience, the circuitry carried over from FIG. 1 to FIG. 3 is similarly labeled.
The circuit illustrated in FIG. 3 first adds a pair of emitter follower transistors 303 and 304, similar to emitter follower transistors 103 and 104. Transistor 303 has a base connected to the emitter of transistor 101. Transistor 304 has a base connected to the emitter of transistor 102. Unlike transistors 103 and 104 which have emitters connected to the negative input terminal I.sub.IN, the emitters of transistors 303 and 304 are connected to a newly added capacitor C* having a value set to equal C.sub.IN.
FIG. 3 also modifies the input stage of FIG. 1 to include a first means 320 and second means 330 for subtracting current. The subtraction means 320 has inputs connected to collectors of transistors 103 and 303 and provides an output connected to a gain node. The subtraction means 330 has inputs connected to collectors of transistors 104 and 304 and provides an output connected to a gain node. Several circuits which are available for the subtraction means 320 and 330 are disclosed in U.S. Pat. No. 5,418,495.
In operation, newly added transistors 303 and 304, subtraction means 320 and 330 and capacitor C* enable cancellation of the effects of C.sub.IN. Subtraction means 320 subtracts the collector current of transistor 303 from the collector current of transistor 103. Similarly, subtraction means 330 subtracts the collector current of transistor 304 from the collector current of transistor 104. Since transistors 103 and 104 have collectors carrying error current components determined by C.sub.IN and transistors 303 and 304 have collector currents determined by capacitor C* set equal to C.sub.IN, by subtracting the collector currents of transistor 303 from 103 and 304 from 104, errors from the signal path due to C.sub.IN are cancelled.